View HY57V283220_237083.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
Revision History
Revision No. 0.1 History Defined Preliminary Specification 1) 2) 3) 4) 5) 6) Modified FBGA Ball Configuration Typo. Changed Functional Block Diagram from A10 to A11. Changed VDD min from 3.0V to 3.135V. Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf. Insert tAC2 Value. Insdrt tRAS & CLK Value. Remark
0.2
0.3 0.4 0.5 0.6 0.7 0.8 0.9
Defined IDD Spec. Delited Preliminary. Changed IDD Spec. 133MHz Speed Added Changed FBGA Package Size from 11x13 to 8x13. 1) Changed VDD min from 3.135V to 3.0V. 2) Changed VIL min from VSSQ-0.3V to -0.3V. Modified of size erra. (Page15) (Equation : 13.00 10 -> 13.00 0.10)
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / July 2004
HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V283220(L)T(P) / HY5V22(L)F(P) is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V283220(L)T(P) / HY5V22(L)F(P) is organized as 4banks of 1,048,576x32. HY57V283220(L)T(P) / HY5V22(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a 2N rule.)
FEATURES
* * * * * * JEDEC standard 3.3V power supply All device pins are compatible with LVTTL interface 86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3 * Internal four banks operation * Burst Read Single Write operation Programmable CAS Latency ; 2, 3 Clocks * * * Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No.
HY57V283220(L)T(P)-5 HY5V22(L)F(P)-5 HY57V283220(L)T(P)-55 HY5V22(L)F(P)-55 HY57V283220(L)T(P)-6 HY5V22(L)F(P)-6 HY57V283220(L)T(P)-7 HY5V22(L)F(P)-7 HY57V283220(L)T(P)-H HY5V22(L)F(P)-H HY57V283220(L)T(P)-8 HY5V22(L)F(P)-8 HY57V283220(L)T(P)-P HY5V22(L)F(P)-P HY57V283220(L)T(P)-S HY5V22(L)F(P)-S
Clock Frequency
200MHz 183MHz 166MHz 143MHz
Organization
Interface
Package
4Banks x 1Mbits x32 133MHz 125MHz 100MHz 100MHz
LVTTL
86TSOP-II 90Ball FBGA
Note) Hynix supports lead free part for each speed grade with same specification.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / July 2004
HY57V283220(L)T(P) / HY5V22(L)F(P)
PIN CONFIGURATION ( HY57V283220(L)T(P) Series)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /W E /C A S /R A S /C S A11 BA0 BA1 A 1 0 /A P A0 A1 A2 DQM2 VDD NC D Q 16 VSSQ D Q 17 D Q 18 VDDQ D Q 19 D Q 20 VSSQ D Q 21 D Q 22 VDDQ D Q 23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS D Q 15 VSSQ D Q 14 D Q 13 VDDQ D Q 12 D Q 11 VSSQ D Q 10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC C LK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC D Q 31 VDDQ D Q 30 D Q 29 VSSQ D Q 28 D Q 27 VDDQ D Q 26 D Q 25 VSSQ D Q 24 VSS
8 6 p in T S O P II 4 0 0 m il x 8 7 5 m i l 0 .5 m m p i n p i t c h
PIN DESCRIPTION
PIN CLK CKE CS BA0, BA1 A0 ~ A11 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
RAS, CAS, WE DQM0~3 DQ0 ~ DQ31 VDD/VSS VDDQ/VSSQ NC
Rev. 0.9 / July 2004
3
HY57V283220(L)T(P) / HY5V22(L)F(P)
Ball CONFIGURATION ( HY5V22(L)F(P) Series)
1 A
DQ26
2
3
4
5
6
7
8
9
DQ24
VSS
VDD
DQ23
DQ21
B
DQ28 VDDQ VSSQ VDDQ VSSQ DQ19
C
VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ
D
VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
E
VDDQ DQ31 NC NC DQ16 VSSQ
F
VSS DQM3 A3 A2 DQM2 VDD
G
A4 A5 A6 A10 A0 A1
H
A7 A8 NC
Top View
NC BA1 A11
J
CLK CKE A9 BA0 /CS /RAS
K
DQM1 NC NC /CAS /WE DQM0
L
VDDQ DQ8 VSS VDD DQ7 VSSQ
M
VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
N
VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
P
DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R
DQ13 DQ15 VSS VDD DQ0 DQ2
Ball DESCRIPTION
PIN CLK CKE CS BA0, BA1 A0 ~ A11 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
RAS, CAS, WE DQM0~3 DQ0 ~ DQ31 VDD/VSS VDDQ/VSSQ NC
Rev. 0.9 / July 2004
4
HY57V283220(L)T(P) / HY5V22(L)F(P)
FUNCTIONAL BLOCK DIAGRAM 1Mbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic & Timer
Refresh Counter
CLK CKE CS RAS CAS WE DQM0 DQM1 DQM2 DQM3
Row Active
1M x32 Bank 3
Row Pre Decoder
1M x32 Bank 2
X decoder X decoder X decoder X decoder X decoder
1M x32 Bank 1 1M x32 Bank 0
DQ0 DQ1
I/O Buffer & Logic
State Machine State Machine
Column Active
Sense AMP & I/O Gate Sense AMP & I/O Gate
X decoder
Memory Cell Array
Column Pre Decoder
DQ30 DQ31
Y decoder
Bank Select
Column Add Counter
A0 A1
Address buffers Address buffers
Address Register
Burst Counter
A11 BA0 BA1
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.9 / July 2004
5
HY57V283220(L)T(P) / HY5V22(L)F(P)
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature Time TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER Symbol 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 260 10 Rating C C V V mA W C Sec Unit
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70C)
Parameter Power Supply Voltage Input high voltage Input low voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 - 0.3 Typ. 3.3 3.0 0 Max 3.6 VDDQ + 0.3 0.8 Unit V V V Note 1 1,2 1,3
Note : 1.All voltages are referenced to VSS = 0V 2.VIH (max) is acceptable 5.6V AC pulse width with 3ns of duration with no input clamp diodes 3.VIL (min) is acceptable -2.0V AC pulse width with 3ns of duration with no input clamp diodes
AC OPERATING CONDITION
Parameter AC input high / low level voltage
(TA=0 to 70C, 3.0V VDD 3.6V, VSS=0V - Note1) Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 30 Unit V V ns V pF 1 Note
Input timing measurement reference level voltage Input rise / fall time Output timing measurement reference level Output load capacitance for access time measurement
Note : 1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF) For details, refer to AC/DC output load circuit
Rev. 0.9 / July 2004
6
HY57V283220(L)T(P) / HY5V22(L)F(P)
CAPACITANCE ( HY57V283220T Series) (TA=25C, f=1MHz, VDD=3.3V)
Parameter Input capacitance CLK A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 Data input / output capacitance DQ0 ~ DQ31 Pin Symbol CI1 CI2 CI/O Min 2.5 2.5 4.0 Max 4.0 4.0 6.5 Unit pF pF pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
Vtt=1.4V
RT=500
RT=50
Output 30pF
Output
Z0 = 50
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (DC operating conditions unless otherwise noted)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL Min. -1 -1 2.4 Max 1 1 0.4 Unit uA uA V V Note 1 2 IOH = -2mA IOL = +2mA
Note : 1.VIN = 0 to 3.6V, All other pins are not under test = 0V 2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.9 / July 2004
7
HY57V283220(L)T(P) / HY5V22(L)F(P)
DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)
Speed Parameter Symbol Test Condition -5 Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 10ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 10ns Input signals are changed one time during 2clks. All other pins VDD0.2V or 0.2V -55 -6 -7 -H -8 -P S Unit Note
Operating Current
IDD1
120
120
110
100
100
100
90
90
mA
1
Precharge Standby Current in power down mode
IDD2P IDD2PS
2 mA 1
IDD2N Precharge Standby Current in non power down mode IDD2NS
14 mA 9
CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 10ns CKE VIL(max), tCK =
CKE VIH(min), CS VIH(min), tCK = 10ns Input signals are changed
IDD3P Active Standby Current in power down mode IDD3PS
7 mA 6
IDD3N Active Standby Current in non power down mode IDD3NS
one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable.
ttCK tCK(min), CL=3 CL=2 230 170 220 160 200 150 180 140
17 mA
13
Burst Mode Operating Current
180 140 2
150 140
130 130 140
130 mA 130 140 mA 2 3 mA 4 1
IDD4
IOL=0mA All banks active
Auto Refresh Current
IDD5
tRC tRC(min), All banks active
Self Refresh Current
IDD6
CKE 0.2V
0.8
Note : 1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V283220T(P)(HY5V22F(P))-5/55/6/7/H/8/P/S 4.HY57V283220LT(P)(HY5V22LF(P))-5/55/6/7/H/8/P/S
Rev. 0.9 / July 2004
8
HY57V283220(L)T(P) / HY5V22(L)F(P)
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
-5 Parameter Symbol Min CAS Latency = 3 CAS Latency = 2 tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 5 1000 10 2 2 1.5 1.5 1 1.5 1 1.5 1 1.5 1 1 4.5 6 4.5 6 10 Max
-55 Min 5.5 1000 10 5 6 5 6 2.5 2.5 2 1.5 1 1.5 1 1.5 1 1.5 1 1 Max Min 6
-6 Max Min 7 1000 10 5.5 6 5.5 6 3 3 2 1.75 1 1.75 1 1.75 1 1.75 1 1 -
-7 Max
-H Min 7.5 Max Min 8 1000 10 5.5 6 5.5 6 3 3 2 1.75 1 1.75 1 1.75 1 1.75 1 1 5.5 6 5.5 6 -10 3 3 2 2 1 2 1 2 1 2 1 1 -
-8 Max Min 10 1000 10 6 6 6 6 3 3 2 2 1 2 1 2 1 2 1 1 -
-P Max Min 10 1000 12 6 6 6 6 3 3 2 2 1 2 1 2 1 2 1 1 -
-S Unit Note Max ns 1000 ns 6 6 6 6 ns ns ns 2 ns ns ns ns ns ns ns ns ns ns ns ns ns 3 1 1 1 1 1 1 1 1 1 1
System clock cycle time
1000
Clock high pulse width Clock low pulse width CAS Latency = 3 CAS Latency = 2
2.25 2.25 2 1.5 1 1.5 1 1.5 1 1.5 1 1 -
Access time from clock
Data-out hold time Data-Input setup time Data-Input hold time Address setup time Address hold time CKE setup time CKE hold time Command setup time Command hold time CLK to data output in low Z-time CAS Latency = 3 CAS Latency = 2
CLK to data output in high Z-time
Note : 1.Assume tR / tF (input rise and fall time ) is 1ns 2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v 3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Rev. 0.9 / July 2004
9
HY57V283220(L)T(P) / HY5V22(L)F(P)
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
-5 Parameter Symbol Min Operation RAS cycle time Auto Refresh RAS to CAS delay tRRC tRCD 55 15 100 K 64 55 tRC 55 Max -
-55 Min 55 Max 100 K 64 Min 60 60 18
-6 Max 100 K 64 Min 63 63 20
-7 Max 100 K 64
-H Min 63 63 20 Max 100 K 64 Min 64 64 20
-8 Max 100 K 64 Min 70 70 20
-P Max 100 K 64 Min 70 70 20
-S Unit Max 100 K 64 ns ns ns Note
16.5
RAS active time
tRAS
38.7
38.7
42
42
42
48
50
50
ns
RAS precharge time RAS to RAS bank active delay CAS to CAS delay Write command to data-in delay Data-in to precharge command Data-in to active command DQM to data-out Hi-Z DQM to data-in mask MRS to new command CAS Latency = 3 CAS Latency = 2
tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF
15 2 1 0 1 4 2 0 2 3 2 1 1 -
16.5 2 1 0 1 4 2 0 2 3 2 1 1 -
18 2 1 0 1 4 2 0 2 3 2 1 1 -
20 2 1 0 1 4 2 0 2 3 2 1 1 -
20 2 1 0 1 4 2 0 2 3 2 1 1 -
20 2 1 0 1 4 2 0 2 3 2 1 1 -
20 20 1 0 1 4 2 0 2 3 2 1 1 -
20 20 1 0 1 4 2 0 2 3 2 1 1 -
ns CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK ms 1
Precharge to data output Hi-Z
Power down exit time Self refresh exit time Refresh Time
Note : 1. A new command can be given tRRC after self refresh exit
Rev. 0.9 / July 2004
10
HY57V283220(L)T(P) / HY5V22(L)F(P)
DEVICE OPERATING OPTION TABLE
HY5xxxxxxxxx(P)-5
CAS Latency 200MHz(5ns) 183MHz(5.5ns) 166MHz(6ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 8CLKs 8CLKs 7CLKs tRC 11CLKs 10CLKs 10CLKs tRP 3CLKs 3CLKs 3CLKs tAC 4.5ns 5ns 5.5ns tOH 1.5ns 2ns 2ns
HY5xxxxxxxxx(P)-55
CAS Latency 183MHz(5.5ns) 166MHz(6ns) 143MHz(7ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 7CLKs 7CLKs 6CLKs tRC 10CLKs 10CLKs 9CLKs tRP 3CLKs 3CLKs 3CLKs tAC 5ns 5.5ns 5.5ns tOH 2ns 2ns 2ns
HY5xxxxxxxxx(P)-6
CAS Latency 166MHz(6ns) 143MHz(7ns) 125MHz(8ns) 3CLKs 3CLKs 3CLKs tRCD 3CLKs 3CLKs 3CLKs tRAS 7CLKs 6CLKs 6CLKs tRC 10CLKs 9CLKs 9CLKs tRP 3CLKs 3CLKs 3CLKs tAC 5.5ns 5.5ns 6ns tOH 2ns 2ns 2.5ns
HY5xxxxxxxxx(P)-7
CAS Latency 143MHz(7ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs tRC 9CLKs 9CLKs 7CLKs tRP 3CLKs 3CLKs 2CLKs tAC 5.5ns 6ns 6ns tOH 2ns 2ns 2ns
HY5xxxxxxxxx(P)-H
CAS Latency 133MHz(7.5ns) 125MHz(8ns) 100MHz(10ns) 3CLKs 3CLKs 2CLKs tRCD 3CLKs 3CLKs 2CLKs tRAS 6CLKs 6CLKs 5CLKs tRC 9CLKs 9CLKs 7CLKs tRP 3CLKs 3CLKs 2CLKs tAC 5.5ns 6ns 6ns tOH 2ns 2ns 2ns
HY5xxxxxxxxx(P)-8
CAS Latency 125MHz(8ns) 100MHz(10ns) 83MHz(12ns) tRCD tRAS tRC tRP tAC tOH
3CLKs 2CLKs 2CLKs
3CLKs 2CLKs 2CLKs
6CLKs 5CLKs 4CLKs
9CLKs 7CLKs 6CLKs
3CLKs 2CLKs 2CLKs
6ns 6ns 6ns
2ns 2ns 2.5ns
Rev. 0.9 / July 2004
11
HY57V283220(L)T(P) / HY5V22(L)F(P)
HY5xxxxxxxxx(P)-P
CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 2CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 2ns 2.5ns 2.5ns
HY5xxxxxxxxx(P)-S
CAS Latency 100MHz(10ns) 83MHz(12ns) 66MHz(15ns) 3CLKs 2CLKs 2CLKs tRCD 2CLKs 2CLKs 2CLKs tRAS 5CLKs 5CLKs 4CLKs tRC 7CLKs 7CLKs 6CLKs tRP 2CLKs 2CLKs 2CLKs tAC 6ns 6ns 6ns tOH 2ns 2.5ns 2.5ns
Rev. 0.9 / July 2004
12
HY57V283220(L)T(P) / HY5V22(L)F(P)
COMMAND TRUTH TABLE
Command Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-Single-WRITE Entry Self Refresh1 Exit CKEn-1 H H H H CKEn X X X X CS L H L L L RAS L X H L H CAS L X H H L WE L X H H H DQM X X X X CA RA L H L H H L X X X A9 Pin High (Other Pins OP code)
3 ADDR
A10/ AP OP code X
BA
Note
V V
H
X
L
H
L
L
X
CA
V X V
H H H H H H L
X X
L L
L H X
H H
L L
X X V
X
H X L H
L L L H L H L H L H L
L L L X H X H X H X V X
L L L X H X H X H X V
H L H X H X H X H X V
X X X X
X
Entry Precharge power down Exit
H
L
X X X
L
H
Clock Suspend
Entry Exit
H L
L H
X X
X
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high 2. X = Dont care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address, Opcode = Operand Code, NOP = No Operation 3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Rev. 0.9 / July 2004
13
HY57V283220(L)T(P) / HY5V22(L)F(P)
PACKAGE INFORMATION (HY57V283220T(P) Series)
400mil 86pin Thin Small Outline Package
Unit : mm(inch)
22.327(0.8790) 22.149(0.8720)
11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960)
0.150(0.0059) 0.050(0.0020)
1.194(0.0470) 0.991(0.0390)
0.50(0.0197)
0.21(0.008) 0.18(0.007)
5deg 0deg
0.597(0.0235) 0.406(0.0160)
0.210(0.0083) 0.120(0.0047)
Rev. 0.9 / July 2004
14
HY57V283220(L)T(P) / HY5V22(L)F(P)
PACKAGE INFORMATION (HY5V22F(P) Series) 90Ball FBGA with 0.8mm of pin pitch (Ball-side view)
6.40 0.80(typ) pin#1
ID
11.20
0.80 typ
13.00 0.10
5.60 0.5 6.50 0.5
3.20 0.5 8.00
4.00 0.5 Ball Size 0.45 0.05mm
1.20max
0.850+/-0.075
seating plane
Rev. 0.9 / July 2004
15

▲Up To Search▲

Price & Availability of HY57V283220

	To Download HY57V283220 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .